Developments in semiconductor technologies over the last few years have allowed the Figure of Merit (FoM) and circuit efficiency to be maintained, or even in some cases improved, as the size of a semiconductor device continually shrinks. One of the modern semiconductor technologies that use a shrinking form factor is embedded die technology. An integrated circuit (IC) chip die, for example, may be located within a core layer of a printed circuit board (PCB), or between layers of a multi-layer circuit board, for example. This technique frees up surface area on the PCB layer surfaces for other circuit components. In some cases, multiple chip dice may be located within different layers or sets of layers of a multi-layer PCB.
Electrical connections between embedded components and outer layers of the PCB are sometimes managed by boring through laminated layers, after encapsulating the components within the layers, to create contacts to the components. In some cases, lasers are used to remove organic/organic glass mixtures or inorganic substrates of the layers. However, these techniques may be too aggressive or invasive for some embedded components. For example, the boring techniques may create less precise connection channels and may cause damage or reliability issues with some embedded components.